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參數(shù)資料
| 型號： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 70/159頁 |
| 文件大小： | 1200K |
| 代理商： | S1C63158D0A010P |
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10
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Further, the reset circuit has incorporated a time authorize circuit that checks the input time of the
simultaneous high input and performs initial reset if that time is the defined time (1 to 2 sec) or more.
If using this function, make sure that the specified ports do not go high at the same time during ordinary
operation.
2.2.3 Oscillation-detect circuit
The oscillation-detect circuit outputs the initial reset signal at power-on until the OSC1 oscillation circuit
starts oscillating, or when the OSC1 oscillation circuit stops oscillating for some reason.
However, for the initial reset at power-on, use a simultaneous high input of the input ports (K00–K03) or
reset terminal, but do not execute it by this function alone.
2.2.4 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.4.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
Table 2.2.4.1 Initial values
Name
Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
CPU core
Symbol
A
B
EXT
X
Y
PC
SP1
SP2
Z
C
I
E
Q
Number of bits
4
8
16
8
1
16
Setting value
Undefined
0110H
Undefined
0
Undefined
Name
RAM
Display memory
Other peripheral circuits
Peripheral circuits
Number of bits
4
–
Setting value
Undefined
2.2.2 Simultaneous high input to terminals K00–K03
Another way of executing initial reset externally is to input a high signal simultaneously to the input
ports (K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at
high level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal
operation. The noise reject circuit does not operate immediately after turning the power on until the
oscillation circuit starts oscillating. Therefore, maintain the specified input port terminals at high level for
at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) after oscillation starts.
Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.2.1 Combinations of input ports
Not use
K00
K01
K00
K01K02
K00
K01K02K03
1
2
3
4
When, for instance, mask option 4 (K00
K01K02K03) is
selected, initial reset is executed when the signals input to the
four ports K00–K03 are all high at the same time. When 2 or 3 is
selected, the initial reset is done when a key entry including a
combination of selected input ports is made.
See Section 4.1, "Memory Map".
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