參數(shù)資料
型號： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 153/159頁
文件大小： 1200K
代理商： S1C63158D0A010P
S1C63808 TECHNICAL MANUAL
EPSON
85
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Data receive procedure
The control procedure and operation during receiving is as follows.
End
RXENx
← 1
No
Yes
Receiving interrupt ?
Yes
Receiving complete ?
Received data reading
from TRXDx0–TRXDx7
RXENx
← 0
RXTRGx
← 1
No
Yes
Error generated ?
Error processing
Data receiving
RXENx
← 0
Resets error flags
PERx, OERx and FERx
No
Fig. 4.10.7.3 Receiving procedure in asynchronous mode
(1) Write "0" in the receive enable register RXENx to set the receiving disable status and to reset the
respective PERx, OERx, FERx flags that indicate parity, overrun and framing errors.
(2) Write "1" in the receive enable register RXENx to set into the receiving enable status.
(3) The shift clock will change to enable from the point where the start bit (low) has been input from the
SINx terminal and the receive data will be synchronized to the rising edge following the second
clock, and will thus be successively incorporated into the shift register.
After data bits have been incorporated, the stop bit is checked and, if it is not high, it becomes a framing
error and the error interrupt factor flag ISERx is set to "1". When interrupt has been enabled, an error
interrupt is generated at this point.
When receiving is completed, data in the shift register is transferred to the receive data buffer and the
receiving complete interrupt flag ISRCx is set to "1". When interrupt has been enabled, a receiving
complete interrupt is generated at this point. (When an overrun error is generated, the interrupt
factor flag ISRCx is not set to "1" and a receiving complete interrupt is not generated.)
If "with parity check" has been selected, a parity check is executed when data is transferred into the
receive data buffer from the shift register and if a parity error is detected, the error interrupt factor
flag is set to "1". When the interrupt has been enabled, an error interrupt is generated at this point just
as in the framing error mentioned above.
(4) Read the received data from TRXDx0–TRXDx7 using receiving complete interrupt.
(5) Write "1" to the receive control bit RXTRGx to inform that the receive data has been read out.
When the following data is received prior to writing "1" to RXTRGx, it is recognized as an overrun
error and the error interrupt factor flag is set to "1". When the interrupt has been enabled, an error
interrupt is generated at this point just as in the framing error and parity error mentioned above.
(6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status
by writing "0" to the receive enable register RXENx, when the receiving is completed.
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