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參數(shù)資料
| 型號： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 147/159頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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80
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Data receive procedure
The control procedure and operation during receiving is as follows.
Data receiving
End
RXENx
← 0, TXENx ← 0
No
Yes
Receiving complete ?
Received data reading
from TRXDx0–TRXDx7
No
Yes
ISRCx = 1 ?
RXENx
← 0
RXTRGx
← 1
RXENx
← 1
No
Yes
Transmitter ready ?
In case of master mode
Fig. 4.10.6.3 Receiving procedure in clock synchronous mode
(1) Write "0" in the receive enable register RXENx and transmit enable register TXENx to reset the
serial interface.
(2) Write "1" in the receive enable register RXENx to set into the receiving enable status.
(3) In case of the master mode, confirm the transmit ready status on the slave side (external serial
input/output device), if necessary. Wait until it reaches the transmit ready status.
(4) Write "1" in the receive control bit RXTRGx and start receiving.
In the master mode, this control causes the synchronous clock to change to enable and is provided
to the shift register for receiving and output from the SCLKx terminal.
In the slave mode, it waits for the synchronous clock to be input from the SCLKx terminal. The
received data input from the SINx terminal is successively incorporated into the shift register in
synchronization with the rising edge of the synchronous clock.
At the point where the data of the 8th bit has been incorporated at the final (8th) falling edge
(when positive polarity is selected) or rising edge (when negative polarity is selected) of the
synchronous clock, the content of the shift register is sent to the receive data buffer and the
receiving complete interrupt factor flag ISRCx is set to "1". When interrupt has been enabled, a
receiving complete interrupt is generated at this point.
(5) Read the received data from TRXDx0–TRXDx7 using receiving complete interrupt.
(6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable
status by writing "0" to the receive enable register RXENx, when the receiving is completed.
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