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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 17/159頁(yè) |
| 文件大小： | 1200K |
| 代理商： | S1C63158D0A010P |
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S1C63808 TECHNICAL MANUAL
EPSON
105
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Integer Multiplier)
4.12.3 Division mode
To perform a division, set the divisor to the source register (SR) and the dividend to the destination
register (DRH and DRL), then write "1" to the calculation mode selection register (CALMD). The division
takes 10 CPU clock cycles from writing "1" to CALMD until the quotient is loaded into the low-order 8
bits (DRL) of the destination register and the remainder is loaded into the high-order 8 bits (DRH) of the
destination register. At the same time the result is loaded, the operation flags (NF, VF and ZF) are up-
dated.
However, when an overflow results (if the quotient exceeds the 8-bit range), the destination register
(DRH and DRL) does not change its contents as it maintains the dividend.
The following shows the conditions that change the operation flag states and examples of division.
N flag:
Set when the MSB of DRL is "1" and reset when it is "0".
V flag:
Set when the quotient exceeds the 8-bit range and reset when it is within the 8-bit range.
Z flag:
Set when the 8-bit value in DRL is 00H and reset when it is not 00H.
<Examples of division>
DRH/DRL (dividend) SR (divisor)
DRL (quotient) DRH (remainder)
NF VF
ZF
1A16H
64H
42H
4EH
0
332CH
64H
83H
00H
1
0
0000H
58H
00H
0
1
2468H
13H
68H
24H
1
0
In the example of "2468H"
÷ "13H" shown above, DRH/DRL maintains the dividend because the quotient
overflows the 8-bit. To get the correct results when an overflow has occurred, perform the division with
two steps as shown below.
1. Divide the high-order 8 bits of the dividend (24H) by the divisor (13H) and then store the quotient
(01H) to memory.
DRH/DRL (dividend) SR (divisor)
DRL (quotient) DRH (remainder)
NF VF
ZF
0024H
13H
01H
11H
0
2. Keep the remainder (11H) in DRH and load the low-order 8 bits of the dividend (68H) to DRL, then
perform division again.
DRH/DRL (dividend) SR (divisor)
DRL (quotient) DRH (remainder)
NF VF
ZF
1168H
13H
EAH
0AH
1
0
The correct result is obtained as the quotient = 01EAH (the first and second results of DRL are merged)
and the remainder = 0AH. However, since the operation flags (NF/VF/ZF) are changed in each step, they
cannot indicate the states according to the final operation results.
Note: Make sure that the division results are correct using software as the hardware does not check.
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