參數(shù)資料
型號: S1C63158D0A010P
元件分類: 微控制器/微處理器
英文描述: 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝: DIE-53
文件頁數(shù): 18/159頁
文件大小: 1200K
代理商: S1C63158D0A010P
106
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Integer Multiplier)
4.12.4 Execution cycle
Both the multiplication and division take 10 CPU cycles for an operation. Therefore, before the results can
be read from the destination register DRH/DRL, wait at least 5 bus cycles after writing to CALMD. The
same applies to reading the operation flags NF/VF/ZF.
The following shows a sample program.
ldb
%ext, src_data@h
ldb
%xl, src_data@l
; Set RAM address for operand
ldb
%ext, au@h
ldb
%yl, au@l
; Set multiplier I/O memory address
;
ldb
%ba, [%x]+
ldb
[%y]+, %ba
; Set data to SR
ldb
%ba, [%x]+
ldb
[%y]+, %ba
; Set data to DRL
ldb
%ba, [%x]+
ldb
[%y]+, %ba
; Set data to DRH
;
ld
[%y], 0b0001
; Start operation (select calculation mode)
;
ldb
%ext, rslt_data@h
ldb
%xl, rslt_data@l
; Set result store address
nop
; Dummy instructions to wait end of operation
;
bit
[%y], 0b0100
jrnz overflow
; Jump to error routine if VF = "1"
;
add
%y, -4
; Set DRL again
;
ldb
%ba, [%y]+
ldb
[%x]+, %ba
; Store result (quotient) into RAM
ldb
%ba, [%y]+
ldb
[%x]+, %ba
; Store result (remainder) into RAM
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