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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 143/159頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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76
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.10.5 Transmit-receive control
Below is a description of the registers which handle transmit-receive control. With respect to transmit-
receive control procedures and operations, please refer to the following sections in which these are
discussed on a mode by mode basis.
Shift register and receive data buffer
Exclusive shift registers for transmitting and receiving are installed in this serial interface. Conse-
quently, duplex communication simultaneous transmit and receive is possible when the asynchronous
system is selected.
Data being transmitted are written to TRXDx0–TRXDx7 and converted to serial through the shift
register and is output from the SOUTx terminal.
In the reception section, a receive data buffer is installed separate from the shift register.
Data being received are input to the SINx terminal and is converted to parallel through the shift
register and written to the receive data buffer.
Since the receive data buffer can be read even during serial input operation, the continuous data is
received efficiently.
However, since buffer functions are not used in clock synchronous mode, be sure to read out data
before the next data reception begins.
Transmit enable register and transmit control bit
For transmit control, use the transmit enable register TXENx and transmit control bit TXTRGx.
The transmit enable register TXENx is used to set the transmit enable/disable status. When "1" is
written to this register to set the transmitting enable status, clock input to the shift register is enabled
and the system is ready to transmit data. In the clock synchronous mode, synchronous clock input/
output from the SCLKx terminal is also enabled.
The transmit control bit TXTRGx is used as the trigger to start transmitting data.
Data to be transmitted is written to the transmit data shift register, and when transmitting prepara-
tions a recomplete, "1" is written to TXTRGx whereupon data transmitting begins.
When interrupt has been enabled, an interrupt is generated when the transmission is completed. If
there is subsequent data to be transmitted it can be sent using this interrupt.
In addition, TXTRGx can be read as a status bit. When set to "1", it indicates transmitting operation,
and "0" indicates transmitting stop.
For details on timing, see the timing chart which gives the timing for each mode.
When not transmitting, set TXENx to "0" to disable transmission.
Receive enable register and receive control bit
For receiving control, use the receive enable register RXENx and receive control bit RXTRGx.
Receive enable register RXENx is used to set receiving enable/disable status. When "1" is written into
this register to set the receiving enable status, clock input to the shift register is enabled and the
system is ready to receive data. In the clock synchronous mode, synchronous clock input/output from
the SCLKx terminal is also enabled. With the above setting, receiving begins and serial data input
from the SINx terminal goes to the shift register.
The operation of the receive control bit RXTRGx is slightly different depending on whether a clock
synchronous system or an asynchronous system is being used.
In clock synchronous system, the receive control bit RXTRGx is used as the trigger to start receiving
data. When received data has been read and the preparation for next data receiving is completed,
write "1" into RXTRGx to start receiving. (When "1" is written to RXTRGx in slave mode, SRDYx is
asserted.)
In asynchronous system, RXTRGx is used to prepare for next data receiving. After reading the re-
ceived data from the receive data buffer, write "1" into RXTRGx to signify that the receive data buffer
is empty. If "1" is not written into RXTRGx, the overrun error flag OERx will be set to "1" when the
next receiving operation is completed. (An overrun error will be generated when receiving is com-
pleted between reading the received data and the writing of "1" to RXTRGx.)
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