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參數(shù)資料
| 型號： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 40/159頁 |
| 文件大小： | 1200K |
| 代理商： | S1C63158D0A010P |
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126
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
(5) When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary
to turn the OSC3 oscillation ON, prior to using the serial interface.
A time interval of 5 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation
stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an
adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiv-
ing of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and
on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 7,
"Electrical Characteristics".)
At initial reset, the OSC3 oscillation circuit is set to OFF status.
(6) Be aware that the maximum clock frequency for the serial interface is limited to 2 MHz.
Sound generator
(1) When using the R01 port as the BZ output port, fix the data register R01 at "1" and the high imped-
ance control register R01HIZ at "0" (data output).
(2) Since it generates a buzzer signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes on/off due to the setting of the BZE register.
(3) The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid
when the normal buzzer output is on (BZE = "1").
Integer multiplier
An operation process takes 10 CPU clock cycles (5 bus cycles) after writing to the calculation mode
selection register CALMD until the operation result is set to the destination register DRH/DRL and
the operation flags. While this operation process, do not read/write from/to the destination register
DRH/DRL and do not read NF/VF/ZF.
SVD circuit
(1) To obtain a stable detection result, the SVD circuit must be on for at least 1 msec. So, to obtain the SVD
detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 1 msec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD circuit should normally be turned off because SVD operation increase current consumption.
Power supply for EPD driver IC
Because at initial reset, the LC3–LC0 register is set to 0000B (VC1 = 1.03 V when 1/3 bias is selected or
1.08 V when 1/2 bias is selected), it is necessary to initialize by the software. Furthermore, the EPD
system voltage circuit is turned off and the VC1–VC3 terminals go to VSS level.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine. Further,
when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all
the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set.
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