
S1C63808 TECHNICAL MANUAL
EPSON
43
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
In the clock synchronous slave mode, all the P10–P13/P20–P23 ports are set to the serial interface input/
output port. In the clock synchronous master mode, P10–P12/P20–P22 are set to the serial interface
input/output port and P13/P23 can be used as an I/O port. In the 8/7-bit asynchronous mode, P10/P20
and P11/P21 are set to the serial interface input/output port and P12/P22 and P13/P23 can be used as
I/O ports.
At initial reset, these registers are set to "0".
(2) I/O port control
P00–P03: P0 I/O port data register (FF42H)
P10–P13: P1 I/O port data register (FF46H)
P20–P23: P2 I/O port data register (FF4AH)
P30–P33: P3 I/O port data register (FF4EH)
P40–P43: P4 I/O port data register (FF52H)
I/O port data can be read and output data can be set through these registers.
When writing data
When "1" is written: High level
When "0" is written: Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,
the terminal goes low (VSS).
Port data can be written also in the input mode.
When reading data
When "1" is read: High level
When "0" is read: Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the register value can be read.
When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal
voltage is low (VSS) the data is "0".
When "with pull-down resistor" has been selected with the mask option and the PUL register is set to "1",
the built-in pull-down resistor goes on during input mode, so that the I/O port terminal is pulled down.
The data registers of the port, which are set for the input/output of the serial interface (P10–P13, P20–
P23), become general-purpose registers that do not affect the input/output.
Note: When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of
the waveform is delayed on account of the time constant of the pull-down resistor and input gate
capacitance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k
(Max.)