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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 122/159頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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S1C63808 TECHNICAL MANUAL
EPSON
57
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
EDIR: Direct input function enable register (FF7BHD3)
Enables the direct input (RUN/LAP) function.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
The direct input function is enabled by writing "1" to EDIR, and then RUN/STOP and LAP control can be
done by external key input. When "0" is written, the direct input function is disabled, and the stopwatch
timer is controlled by the software only.
Further the function switching is actually done by synchronizing with the falling edge of fOSC1/32 (1,024
Hz) after the data is written to this register (after 977 sec maximum).
At initial reset, this register is set to "0".
SWDIR: Direct input switch register (FF06HD2)
Switches the direct-input key assignment for the K00 and K01 ports.
When "1" is written: K00 = LAP, K01 = RUN/STOP
When "0" is written: K00 = RUN/STOP, K01 = LAP
Reading: Valid
The direct-input key assignment is selected using this register. The K00 and K01 port statuses are input to
the stopwatch timer as the RUN/STOP and LAP inputs according to this selection.
At initial reset, this register is set to "0".
DKM0–DKM2: Direct key mask selection register (FF7BHD0–D2)
Selects a combination of the key inputs for concurrence judgment with RUN and LAP inputs when the
direct input function is set.
Table 4.8.7.2 Key mask selection
DKM2
0
1
DKM1
0
1
0
1
DKM0
0
1
0
1
0
1
0
1
Mask key combination
None (at initial reset)
K02
K02, K03
K02, K03, K10
K10
K10, K11
K10, K11, K12
K10, K11, K12, K13
When the concurrence is detected, RUN and LAP inputs cannot be accepted until the concurrence is
released.
At initial reset, this register is set to "0".
SWRST: Stopwatch timer reset (FF7CHD0)
This bit resets the stopwatch timer.
When "1" is written: Stopwatch timer reset
When "0" is written: No operation
Reading: Always "0"
The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN
status, operation restarts immediately. Also, in the STOP status the reset data is maintained.
Since this reset does not affect the capture buffer, the capture buffer data in hold status is not cleared and
is maintained.
This bit is write-only, and is always "0" at reading.
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