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參數(shù)資料
| 型號： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 154/159頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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86
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Receive error
During receiving the following three types of errors can be detected by an interrupt.
(1) Parity error
When writing "1" to the EPRx register to select "with parity check", a parity check (vertical parity
check) is executed during receiving. After each data bit is sent a parity check bit is sent. The parity
check bit is a "0" or a "1". Even parity checking will cause the sum of the parity bit and the other
bits to be even. Odd parity causes the sum to be odd. This is checked on the receiving side.
The parity check is performed when data received in the shift register is transferred to the receive
data buffer. It checks whether the parity check bit is a "1" or a "0" (the sum of the bits including the
parity bit) and the parity set in the PMDx register match. When it does not match, it is recognized
as an parity error and the parity error flag PERx and the error interrupt factor flag ISERx are set to
"1".
When interrupt has been enabled, an error interrupt is generated at this point.
The PERx flag is reset to "0" by writing "1".
Even when this error has been generated, the received data corresponding to the error is trans-
ferred in the receive data buffer and the receive operation also continues.
The received data at this point cannot assured because of the parity error.
(2) Framing error
In asynchronous transfer, synchronization is adopted for each character at the start bit ("0") and
the stop bit ("1"). When receiving has been done with the stop bit set at "0", the serial interface
judges the synchronization to be off and a framing error is generated. When this error is gener-
ated, the framing error flag FERx and the error interrupt factor flag ISERx are set to "1". When
interrupt has been enabled, an error interrupt is generated at this point.
The FERx flag is reset to "0" by writing "1".
Even when this error has been generated, the received data corresponding to the error is trans-
ferred in the receive data buffer and the receive operation also continues. However, even when it
does not become a framing error with the following data receiving, such data cannot be assured.
(3) Overrun error
When the next data is received before "1" is written to RXTRGx, an overrun error will be gener-
ated, because the previous receive data will be overwritten. When this error is generated, the
overrun error flag OERx and the error interrupt factor flag ISERx are set to "1". When interrupt has
been enabled, an error interrupt is generated at this point. The OERx flag is reset to "0" by writing
"1" into it.
Even when this error has been generated, the received data corresponding to the error is trans-
ferred in the receive data buffer and the receive operation also continues.
Furthermore, when the timing for writing "1" to RXTRGx and the timing for the received data
transfer to the receive data buffer overlap, it will be recognized as an overrun error.
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