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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 140/159頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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S1C63808 TECHNICAL MANUAL
EPSON
73
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SINx and SOUTx are serial data input and output terminals which function identically in clock synchro-
nous system and asynchronous system. SCLKx is exclusively for use with clock synchronous system and
functions as a synchronous clock input/output terminal. SRDYx is exclusively for use in clock synchro-
nous slave mode and functions as a send-receive ready signal output terminal.
When asynchronous system is selected, since SCLKx and SRDYx are superfluous, the I/O port terminals
P12/P22 and P13/P23 can be used as I/O ports.
In the same way, when clock synchronous master mode is selected, since SRDYx is superfluous, the I/O
port terminal P13/P23 can be used as I/O port.
4.10.2 Mask option
Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13, P20–P23), the
mask option that selects the terminal specification for the I/O port is also applied to the serial interface.
Output specification
The output specification of the terminals SOUTx, SCLKx (for clock synchronous master mode) and
SRDYx (for clock synchronous slave mode) that are used as output in the input/output port of the
serial interface is respectively selected by the mask options of P11/P21, P12/P22 and P13/P23. Either
complementary output or P-channel open drain output can be selected as the output specification.
However, when P-channel open drain output is selected, do not apply a voltage exceeding the power
supply voltage to the terminal.
Pull-down resistor
The pull-down resistors for the SINx terminal and the SCLKx terminal (during slave mode) that are
used as input terminals can be selected by mask option. The pull-down resistor can be added by the
mask options of P10/P20 and P12/P22. When "gate direct" is selected, take care that the floating
status does not occur.
Polarity of synchronous clock and ready signal in clock synchronous slave mode
Polarity of the synchronous clock and the ready signal that is output in the clock synchronous slave
mode can be selected from either positive polarity (high active, SCLKx & SRDYx) or negative polarity
___________
(low active, SCLKx & SRDYx).
When operating the serial interface in the slave mode, the synchronous clock is input from a external
device. Be aware that the terminal specification is pull-down only and a pull-up resistor cannot be
built in if negative polarity is selected.
In the following explanation, it is assumed that positive polarity (SCLKx, SRDYx) has been selected.
4.10.3 Transfer modes
There are four transfer modes for the serial interface and mode selection is made by setting the two bits of
the mode selection registers SMDx0 and SMDx1 as shown in the table below.
Table 4.10.3.1 Transfer modes
SMDx1
SMDx0
Mode
1
0
1
0
1
0
8-bit asynchronous
7-bit asynchronous
Clock synchronous slave
Clock synchronous master
Table 4.10.3.2 Terminal settings corresponding to each transfer mode
Mode
SIN
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
P13/P23
Output
P13/P23
SOUTx
SCLKx
SRDYx
P12/P22
Input
Output
Input
At initial reset, transfer mode is set to clock synchronous master mode.
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