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參數(shù)資料
| 型號： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 128/159頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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62
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.9.3 Setting the input clock
A prescaler is provided for each timer. The prescaler generates the input clock for the timer by dividing
the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software for
each timer individually.
The input clock is set in the following sequence.
Selection of source clock
Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection register CKSELx; when "0" is written to the register, OSC1 is selected and
when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation on, prior to using the programmable timer. However the OSC3 oscillation circuit requires a
time at least 5 msec from turning the circuit on until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit on to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in off state.
Selection of prescaler division ratio
Select the division ratio for each prescaler from among 4 types. This selection is done using the
prescaler division ratio selection register PTPSx0/PTPSx1. Table 4.9.3.1 shows the correspondence
between the setting value and the division ratio.
Table 4.9.3.1 Selection of prescaler division ratio
PTPSx1
1
0
PTPSx0
1
0
1
0
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
By writing "1" to the PTRUNx register, the prescaler inputs the source clock and outputs the clock
divided by the selected division ratio. The counter starts counting down by inputting the clock.
4.9.4 Event counter mode (timer 0)
Timer 0 has an event counter function that counts an external clock input to the input port K13. This
function is selected by writing "1" to timer 0 counter mode selection register EVCNT. At initial reset,
EVCNT is set to "0" and timer 0 is configured as a normal timer that counts the internal clock.
In the event counter mode, the clock is supplied to timer 0 from outside the IC, therefore, the settings of
the timer 0 prescaler division ratio selection register PTPS00–PTPS01 and the settings of the timer 0
source clock selection register CKSEL0 become invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the
timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling
edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown in
Figure 4.9.4.1.
K13 input
Count data
n
n-1
n-2
n-3
n-4
n-5
n-6
PLPOL
EVCNT
01
1
PTRUN0
Fig. 4.9.4.1 Timing chart in event counter mode
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