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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 69/159頁(yè) |
| 文件大小： | 1200K |
| 代理商： | S1C63158D0A010P |
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S1C63808 TECHNICAL MANUAL
EPSON
9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C63808 circuits, initial reset must be executed. There are three ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous high input to terminals K00–K03 (mask option setting)
(3) Internal initial reset by the oscillation-detect circuit
When the power is turned on, be sure to initialize using the reset function (1) or (2). It is not guaranteed
that the circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
RESET
K00
K01
K02
K03
OSC2
OSC1
oscillation
circuit
Noise
reject
circuit
Internal
initial
reset
Time
authorize
circuit
Oscillation
detect circuit
VSS
Mask option
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a high level (VDD). After that the
initial reset is released by setting the reset terminal to a low level (VSS) and the CPU starts operation.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when fOSC1 = 32.768 kHz) is needed until the internal initial
reset is released after the reset terminal goes to low level. Be sure to maintain a reset input of 0.1 msec or
more. However, when turning the power on, the reset terminal should be set at a high level as in the
timing shown in Figure 2.2.1.1.
Note that a reset pulse shorter than 100 nsec is rejected as noise.
VDD
RESET
2.0 msec or more
1.8 V
0.5VDD
0.9VDD or more (high level)
Power on
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.9VDD or more (high level) until the supply voltage becomes 1.8 V
or more.
After that, a level of 0.5VDD or more should be maintained more than 2.0 msec.
The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the
resistor is used or not.
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