參數(shù)資料
型號(hào)： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 156/159頁
文件大?。?/td> 1200K
代理商： S1C63158D0A010P
88
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Data
bus
Interrupt
request
Address
Error generation
Interrupt factor
flag ISERx
Address
Interrupt mask
register EISERx
Address
Receive completion
Interrupt factor
flag ISRCx
Address
Interrupt mask
register EISRCx
Address
Transmit completion
Interrupt factor
flag ISTRx
Address
Interrupt mask
register EISTRx
Fig. 4.10.8.1 Configuration of serial interface interrupt circuit
Transmit completion interrupt
This interrupt factor is generated at the point where the sending of the data written into the shift
register has been completed and sets the interrupt factor flag ISTRx to "1". When set in this manner, if
the corresponding interrupt mask register EISTRx is set to "1" and the CPU is set to interrupt enabled
status (I flag = "1"), an interrupt will be generated to the CPU.
When the interrupt mask register EISTRx has been set to "0" and interrupt has been disabled, no
interrupt is generated to the CPU. Even in this case, the interrupt factor flag ISTRx is set to "1".
The interrupt factor flag ISTRx is reset to "0" by writing "1".
The following transmitting data can be set and the transmitting can be started (writing "1" to
TXTRGx) after this interrupt factor occurs.
Receive completion interrupt
This interrupt factor is generated at the point where receiving has been completed and the receive
data incorporated into the shift register has been transferred into the receive data buffer and it sets the
interrupt factor flag ISRCx to "1". When set in this manner, if the corresponding interrupt mask
register EISRCx is set to "1" and the CPU is set to interrupt enabled status (I flag = "1"), an interrupt
will be generated to the CPU.
When the interrupt mask register EISRCx has been set to "0" and interrupt has been disabled, no
interrupt is generated to the CPU. Even in this case, the interrupt factor flag ISRCx is set to "1".
The interrupt factor flag ISRCx is reset to "0" by writing "1".
The generation of this interrupt factor allows reading of the received data.
Also, the interrupt factor flag ISRCx is set to "1" when a parity error or framing error is generated.
Error interrupt
This interrupt factor is generated at the point where a parity error, framing error or overrun error is
detected during receiving and it sets the interrupt factor flag ISERx to "1". When set in this manner, if
the corresponding interrupt mask register EISERx is set to "1" and the CPU is set to interrupt enabled
status (I flag = "1"), an interrupt will be generated to the CPU.
When the interrupt mask register EISERx has been set to "0" and interrupt has been disabled, an
interrupt is not generated to the CPU. Even in this case, the interrupt factor flag ISERx is set to "1".
The interrupt factor flag ISERx is reset to "0" by writing "1".
Since all three types of errors result in the same interrupt factor, you should identify the error that has
been generated by the error flags PERx (parity error), OERx (overrun error) and FERx (framing error).
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