參數資料
型號: PSD4256G6V-10UIT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數: 85/127頁
文件大?。?/td> 1091K
代理商: PSD4256G6V-10UIT
Complex PLD (CPLD)
PSD4256G6V
Figure 14.
CPLD output macrocell
17.6
Input macrocells (IMC)
The CPLD has 24 input macrocells (IMC), one for each pin on Ports A, B, and C. The
architecture of the input macrocells (IMC) is shown in Figure 15: Input macrocell. The input
macrocells (IMC) are individually configurable, and can be used as a latch, register, or to
pass incoming port signals prior to driving them onto the PLD input bus. The outputs of the
input macrocells (IMC) can be read by the MCU through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each
product term output is used to latch or clock four input macrocells (IMC). Port inputs 3-0 can
be controlled by one product term and 7-4 by another.
Configurations for the input macrocells (IMC) are specified by PSDsoft (see Application
Note AN1171). Outputs of the input macrocells (IMC) can be read by the MCU via the IMC
buffer. See Figure 20 to Figure 30 for examples of the basic connections between the PSD
and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for
which they are configured. The MCU bus interface is specified using the I/O ports. (See
PT
ALLOCATOR
MASK
REG.
PT CLK
PT
CLKIN
FEEDBACK (.FB)
PORT INPUT
AND
ARRAY
PLD
INPUT
BUS
MUX
POLARITY
SELECT
LD
IN
CLR
Q
PR
DIN
COMB/REG
SELECT
PORT
DRIVER
INPUT
MACROCELL
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
CLEAR (.RE)
PROGRAMMABLE
FF (D / T/JK /SR)
WR
ENABLE (.OE)
PRESET(.PR)
RD
MACROCELL CS
AI04946
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