參數(shù)資料
型號: PSD4256G6V-10UIT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 3/127頁
文件大小: 1091K
代理商: PSD4256G6V-10UIT
In-circuit programming using the serial interface
PSD4256G6V
The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations
if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft). However, Reset
(RESET) will prevent or interrupt JTAG operations if the JTAG Enable register (as shown in
Table 21) is used to enable the JTAG pins.
The PSD supports JTAG In-System-Programmability (ISP) commands, but not Boundary
Scan. ST’s PSDsoft software tool and FlashLINK JTAG programming cable implement the
JTAG In-System-Programmability (ISP) commands.
22.2
JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received
over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed
Program and Erase cycles by indicating status on PSD pins instead of having to scan the
status out serially using the standard JTAG channel. See application note AN1153.
TERR indicates if an error has occurred when erasing a sector or programming in Flash
memory. This signal goes Low (active) when an Error condition occurs, and stays Low until
a specific JTAG command is executed or a Reset (RESET) pulse is received after an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4) described in Section 6.2.2: Ready/Busy
(PE4). TSTAT is High when the PSD3200 Family device is in Read mode (primary Flash
memory and secondary Flash memory contents can be read). TSTAT is Low when Flash
memory Program or Erase cycles are in progress, and also when data is being written to the
secondary Flash memory.
TSTAT and TERR can be configured as open-drain type signals with a JTAG command.
Note:
The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG
signals are dedicated by an NVM Configuration bit (via PSDsoft). However, Reset (Reset)
prevents or interrupts JTAG operations if the JTAG Enable register (as shown in Table 21) is
used to enable the JTAG signals.
22.3
Security and Flash memory protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG port. When using the JTAG port, only a Full Chip Erase command is allowed.
All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the
device to a non-secured blank state. The Security bit can be set in PSDsoft.
All primary Flash memory and secondary Flash memory sectors can individually be sector
protected against erasure. The sector protect bits can be set in PSDsoft.
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