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參數(shù)資料
| 型號： | PSD4256G6V-10UIT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 63/127頁 |
| 文件大?。?/td> | 1091K |
| 代理商： | PSD4256G6V-10UIT |
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Programming Flash memory
PSD4256G6V
8
Programming Flash memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. Although erasing Flash memory occurs on a sector or
device basis, programming Flash memory occurs on a word basis.
The primary and secondary Flash memories require the MCU to send an instruction to
program a word or to erase sectors (see Table 29: 16-bit instructions and Table 30: 8-bit
Once the MCU issues a Flash memory Program or Erase instruction, it must check the
status bits for completion. The embedded algorithms that are invoked inside the PSD
support several means to provide status to the MCU. Status may be checked using any of
three methods: data polling, data toggle, or Ready/Busy (PE4) signal.
8.1
Data polling
Polling on the Data Polling bit (DQ7/DQ15) is a method of checking whether a Program or
Erase cycle is in progress or has completed. Figure 5 shows the data polling algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the word to be programmed in Flash memory to
check the status. The Data Polling bit (DQ7/DQ15) becomes the complement of the
corresponding bit of the original data word to be programmed. The MCU continues to poll
this location, comparing data and monitoring the Error Flag bit (DQ5/DQ13). When the Data
Polling bit (DQ7/DQ15) matches the corresponding bit of the original data, and the Error
Flag bit (DQ5/DQ13) remains '0,' the embedded algorithm is complete. If the Error Flag bit
(DQ5/DQ13) is '1,' the MCU should test the Data Polling bit (DQ7/DQ15) again since the
Data Polling bit (DQ7/DQ15) may have changed simultaneously with the Error Flag bit
(DQ5/DQ13) (see Figure 5).
The Error Flag bit (DQ5/DQ13) is set if either an internal timeout occurred while the
embedded algorithm attempted to program the location or if the MCU attempted to program
a '1' to a bit that was not erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the word that was written to the Flash
memory with the word that was intended to be written.
When using the data polling method during an Erase cycle, Figure 5 still applies. However,
the Data Polling bit (DQ7/DQ15) is '0' until the Erase cycle is complete. A '1' on the Error
Flag bit (DQ5/DQ13) indicates a timeout condition on the Erase cycle, a 0 indicates no error.
The MCU can read any even location within the sector being erased to get the Data Polling
bit (DQ7/DQ15) and the Error Flag bit (DQ5/DQ13).
PSDsoft generates ANSI C code functions that implement these Data polling algorithms.
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