參數(shù)資料
型號(hào)： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 109/127頁
文件大?。?/td> 1091K
代理商： PSD4256G6V-10UIT
I/O ports
PSD4256G6V
Table 41.
Port operating modes
Port mode
Port A
Port B
Port C
Port D
Port E
Port F
Port G
MCU I/O
Yes
PLD I/O
McellA output
McellB outputs
Additional Ext. CS outputs
PLD Inputs
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Address Out
No
Yes (A7 – 0) Yes (A7 – 0)
Yes (A7 – 0)
or (A15 – 8)
Address In
Yes
No
Yes
No
Data Port
No
Yes
Peripheral I/O
Yes
No
Yes
No
Yes
No
JTAG ISP
No
Yes(1)
No
MCU RESET mode(2)
No
Yes
1.
Can be multiplexed with other I/O functions.
2.
Available to Motorola 16-bit 683xx and HC16 families of MCUs.
Table 42.
Port operating mode settings(1)
Mode
Defined in PSDsoft
Control
register
setting
Direction
register
setting
VM register
setting
JTAG enable
MCU I/O
Declare pins only
0(2)
1 = output,
0 = input(3)
N/A
PLD I/O
Declare pins and
Logic equations
N/A
N/A
Data Port (Port F, G)
Selected for MCU with
non-multiplexed bus
N/A
Address Out
(Port E, F, G)
Declare pins only
1
N/A
Address In
(Port A, B, C, D, F)
Declare pins or Logic
equation for input
macrocells
N/A
Peripheral I/O
(Port F)
Logic equations
(PSEL0 and PSEL1)
N/A
PIO bit = 1
N/A
JTAG ISP(4)
Declare pins only
N/A
JTAG_Enable
MCU RESET mode
Specific pin logic level
N/A
1.
N/A = Not Applicable
2.
Control register setting is not applicable to Ports A, B and C.
3.
The direction of the Port A,B,C, and F pins are controlled by the Direction register ORed with the individual output enable
product term (.oe) from the CPLD AND Array.
4.
Any of these three methods enables the JTAG pins on Port E.
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