參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 36/127頁
文件大?。?/td> 1091K
代理商： PSD4256G6V-10UIT
Description
PSD4256G6V
RESET
39
I
Active Low input. Resets I/O ports, PLD macrocells and some of the Configuration
registers and JTAG registers. Must be Low at Power-up. RESET also aborts any
Flash memory program or erase cycle that is currently in progress.
PA0-PA7
51-58
I/O
CMOS
or
Open
Drain
These pins make up Port A. These port pins are configurable and can have the
following functions:
– MCU I/O – standard output or input port;
– CPLD macrocell (McellA0-McellA7) outputs; and
– Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above)
PB0-PB7
61-68
I/O
CMOS
or
Open
Drain
These pins make up Port B. These port pins are configurable and can have the
following functions:
– MCU I/O – standard output or input port;
– CPLD macrocell (McellB0-McellB7) outputs; and
– Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PC0-PC7
41-48
I/O
CMOS
These pins make up Port C. These port pins are configurable and can have the
following functions:
– MCU I/O – standard output or input port;
– External Chip Select (ECS0-ECS7) outputs; and
– Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
PD0
79
I/O
CMOS
or
Open
Drain
PD0 pin of Port D. This port pin can be configured to have the following functions:
– ALE/AS input – latches address on ADIO0-ADIO15;
–AS input – latches address on ADIO0-ADIO15 on the rising edge;
– MCU I/O – standard output or input port; and
– Transparent PLD input (can also be PLD input for address A16 and above).
PD1
80
I/O
CMOS
or
Open
Drain
PD1 pin of Port D. This port pin can be configured to have the following functions:
– MCU I/O – standard output or input port;
– Transparent PLD input (can also be PLD input for address A16 and above); and
– CLKIN – clock input to the CPLD macrocell, the APD Unit’s Power-down counter,
and the CPLD AND Array.
PD2
1
I/O
CMOS
or
Open
Drain
PD2 pin of Port D. This port pin can be configured to have the following functions:
– MCU I/O – standard output or input port;
– Transparent PLD input (can also be PLD input for address A16 and above); and
– PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory
and I/O. When High, the PSD memory blocks are disabled to conserve power. The
falling edge of this signal can be used to get the device out of Power-down mode.
PD3
2
I/O
CMOS
or
Open
Drain
PD3 pin of Port D. This port pin can be configured to have the following functions:
– MCU I/O – standard output or input port;
– Transparent PLD input (can also be PLD input for address A16 and above); and
–WRH – for 16-bit data bus, WRITE to high byte, active low.
Table 2.
LQFP80 pin description (continued)
Pin
name(1)
Pin
Type
Description
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