參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 123/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
Power management
20.5
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft as PSD Chip Select Input (CSI). When Low, the
signal selects and enables the internal primary Flash memory, secondary Flash memory,
SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A High on PSD
Chip Select Input (CSI, PD2) disables the primary Flash memory, secondary Flash memory,
and SRAM, and reduces the PSD power consumption. However, the PLD and I/O signals
remain operational when PSD Chip Select Input (CSI, PD2) is High.
There may be a timing penalty when using PSD Chip Select Input (CSI, PD2) depending on
the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 70.
20.6
Input clock
The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power
consumption. CLKIN (PD1) is an input to the PLD AND Array and the output macrocells
(OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the macrocells block by setting bits 4 or 5 to a 1 in PMMR0.
Figure 37.
Enable Power-down flowchart
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 0 to 6.
AI04940
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