參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 81/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
Complex PLD (CPLD)
Figure 13.
Macrocell and I/O port
17.1
Output macrocell (OMC)
Eight of the output macrocells (OMC) are connected to Ports A pins and are named as
McellA0-McellA7. The other eight macrocells are connected to Ports B pins and are named
as McellB0-McellB7.
The output macrocells (OMC) architecture is shown in Figure 14: CPLD output macrocell.
As shown in the figure, there are native product terms available from the AND Array, and
borrowed product terms available (if unused) from other output macrocells (OMC). The
polarity of the product term is controlled by the XOR gate. The output macrocells (OMC) can
implement either sequential logic, using the flip-flop element, or combinatorial logic. The
multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer
output can drive a port pin and has a feedback path to the AND Array inputs.
The flip-flop in the output macrocells (OMC) block can be configured as a D, T, JK, or SR
type in the PSDsoft program. The flip-flop’s clock, preset, and clear inputs may be driven
from a product term of the AND Array. Alternatively, the external CLKIN (PD1) signal can be
used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active High inputs. Each clear input can use up to two
product terms.
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
D
Q
G
D
QD
WR
PDR
DATA
PRODUCT TERM
ALLOCATOR
DIR
REG.
SELECT
INPUT
PRODUCT TERMS
FROM OTHER
MACROCELLS
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
CLOCK
SELECT
PR DI LD
D/T
CK
CL
Q
D/T/JK FF
SELECT
PT CLEAR
PT
CLOCK
GLOBAL
CLOCK
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
COMB.
/REG
SELECT
PLD
INPUT
BUS
PLD
INPUT
BUS
MCU ADDRESS / DATA BUS
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
AND
ARRAY
CPLD OUTPUT
I/O PIN
AI04945
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