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| 型號(hào)： | PSD4256G6V-10UIT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁(yè)數(shù)： | 105/127頁(yè) |
| 文件大?。?/td> | 1091K |
| 代理商： | PSD4256G6V-10UIT |
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PSD4256G6V
I/O ports
79/127
19
I/O ports
There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each port pin is
individually user configurable, thus allowing multiple functions per port. The ports are
configured using PSDsoft or by the MCU writing to on-chip registers in the CSIOP space.
The topics discussed in this section are:
●
General port architecture
●
Port operating modes
●
Port Configuration registers (PCR)
●
Port data registers
●
Individual port functionality.
19.1
General port architecture
The general architecture of the I/O port block is shown in Figure 31. Individual port
purpose for a port pin has been defined, that pin is no longer available for other purposes.
Exceptions are noted.
As shown in Figure 31, the ports contain an output multiplexer whose select signals are
driven by the configuration bits in the Control registers (Ports E, F and G only) and PSDsoft
Configuration. Inputs to the multiplexer include the following:
●
Output data from the Data Out register
●
Latched address outputs
●
CPLD macrocell output
●
External Chip Select from the CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and
can be read by the MCU. The Data Out and macrocell outputs, Direction register and
Control register, and port pin input are all connected to the Port Data Buffer (PDB).
The port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND Array enable product term and the Direction register.
If the enable product term of any of the Array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDabel file, the Direction register has sole control of the
buffer that drives the port pin.
The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB)
feedback path allows the MCU to check the contents of the registers.
Ports A, B, and C have embedded input macrocells (IMC). The Input macrocells (IMC) can
be configured as latches, registers, or direct inputs to the PLDs. The latches and registers
are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array.
The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the
MCU. See Section 17.6: Input macrocells (IMC).
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