參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 125/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
RESET timing and device status at RESET
21
RESET timing and device status at RESET
21.1
Power-on RESET
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO (minimum
1ms) after VCC is steady. During this period, the device loads internal configurations, clears
some of the registers and sets the Flash memory into Operating mode. After the rising edge
of Reset (RESET), the PSD remains in the RESET mode for an additional period, tOPR
(maximum 120 ns), before the first memory access is allowed.
The PSD Flash memory is reset to the Read mode upon Power-up. Sector Select (FS0-
FS15 and CSBOOT0-CSBOOT3) must all be Low, WRITE Strobe (WR/WRL, CNTL0) High,
during Power-on RESET for maximum security of the data contents and to remove the
possibility of data being written on the first edge of WRITE Strobe (WR/WRL, CNTL0). Any
Flash memory WRITE cycle initiation is prevented automatically when VCC is below VLKO.
21.2
Warm RESET
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, tNLNH (minimum 150 ns). The same tOPR period is needed before the device is
operational after Warm RESET. Figure 38 shows the timing of the Power-up and Warm
RESET.
21.3
I/O pin, register and PLD Status at RESET
Table 53 shows the I/O pin, register and PLD status during Power-on RESET, Warm RESET
and Power-down mode. PLD outputs are always valid during Warm RESET, and they are
valid in Power-on RESET once the internal PSD Configuration bits are loaded. This loading
of PSD is completed typically long before the VCC ramps up to operating level. Once the
PLD is active, the state of the outputs are determined by equations specified in PSDsoft.
21.4
RESET of Flash memory Erase and Program cycles
An external Reset (RESET) also resets the internal Flash memory state machine. During a
Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the
Flash memory to the Read mode within a period of tNLNH-A (minimum 25 s).
Figure 38.
Reset (RESET) timing
tNLNH-PO
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
tOPR
VCC
V
CC(min)
Power-On Reset
Warm Reset
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