參數(shù)資料
型號(hào)： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 77/127頁
文件大?。?/td> 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
PLDs
15
PLDs
The PLDs bring programmable logic functionality to the PSD. After specifying the logic for
the PLDs using PSDsoft, the logic is programmed into the device and available upon Power-
up.
The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The
PLDs are briefly discussed in the next few paragraphs, and in more detail in the following
sections. Figure 11: PLD diagram shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory, registers,
and I/O ports Select signals.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The
CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are
The Turbo bit in PSD
The PLDs in the PSD3200 Family can minimize power consumption by switching to
standby when inputs remain unchanged for an extended time of about 70ns. Resetting the
Turbo bit to '0' (bit 3 of the PMMR0 register) automatically places the PLDs into standby if no
inputs are changing. Turning the Turbo mode off increases propagation delays while
reducing power consumption. See Section 20: Power management, on how to set the Turbo
bit.
Additionally, five bits are available in the PMMR2 register to block MCU control signals from
entering the PLDs. This reduces power consumption and can be used only when these
MCU control signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Table 32.
DPLD and CPLD Inputs
Input source
Input name
Number of
signals
MCU address bus(1)
A15-A0
16
MCU control signals
CNTL0-CNTL2
3
Reset
RST
1
Power-down
PDN
1
Port A input macrocells
PA7-PA0
8
Port B input macrocells
PB7-PB0
8
Port C input macrocells
PC7-PC0
8
Port D inputs
PD3-PD0
4
Port F inputs
PF7-PF0
8
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