參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 42/127頁
文件大?。?/td> 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
PSD architectural overview
2.4
MCU bus interface
The PSD easily interfaces with most 8-bit or 16-bit MCUs, either with multiplexed or non-
multiplexed address/data buses. The device is configured to respond to the MCU’s control
pins, which are also used as inputs to the PLDs.
2.5
ISP via JTAG port
In-system programming (ISP) can be performed through the JTAG signals on Port E. This
serial interface allows complete programming of the entire PSD module device. A blank
device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI,
TDO) can be multiplexed with other functions on Port E. Table 4: JTAG signals on port E
indicates the JTAG pin assignments.
2.6
In-system programming (ISP)
Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can
be programmed or erased without the use of the MCU.
2.7
In-application programming (IAP)
The primary Flash memory can also be programmed, or re-programmed, in-system by the
MCU executing the programming algorithms out of the secondary Flash memory, or SRAM.
The secondary Flash memory can be programmed the same way by executing out of the
PSD indicates which programming methods can program different functional blocks of the
PSD.
Table 3.
PLD I/O
Name
Inputs
Outputs
Product terms
Decode PLD (DPLD)
82
17
43
Complex PLD (CPLD)
82
24
150
Table 4.
JTAG signals on port E
Port E pins
JTAG signal
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
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