參數(shù)資料
型號: PSD4256G6V-10UIT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 116/127頁
文件大?。?/td> 1091K
代理商: PSD4256G6V-10UIT
PSD4256G6V
I/O ports
19.23
Port D – functionality and structure
Port D has four I/O pins. See Figure 34. Port D can be configured to perform one or more of
the following functions:
MCU I/O mode
CPLD Input – direct input to the CPLD, no input macrocells (IMC)
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
Address Strobe (ALE/AS, PD0)
CLKIN (PD1) as input to the macrocells Flip-flops and APD counter
PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory,
SRAM and CSIOP.
WRITE-Enable High-byte (WRH, PD3) input, or as DBE input from a MC68HC912.
Figure 34.
Port D structure
INTERNAL
DATA
BUS
DATA OUT
Register
DQ
WR
READ MUX
P
D
B
CPLD - INPUT
DIR Register
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI04937
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