參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 101/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
MCU bus interface
18.13
80C251
The Intel 80C251 MCU features a user-configurable bus interface with four possible bus
configurations, as shown in Table 40. The first configuration is 80C31-compatible, and the
bus interface to the PSD is identical to that shown in Figure 26. The second and third
configurations have the same bus connection as shown in Figure 27. There is only one
READ Strobe (PSEN) connected to CNTL1 on the PSD. The A16 connection to PA0 allows
for a larger address input to the PSD. The fourth configuration is shown in Figure 28. READ
Strobe (RD) is connected to CNTL1 and Program Select Enable (PSEN) is connected to
CNTL2.
The 80C251 has two major operating modes:
18.13.1
Page mode
Data (D7-D0) is multiplexed with address (A15-A8). In a bus cycle where there is a Page hit,
Address Strobe (ALE/AS, PD0) is not active and only addresses (A7-A0) are changing.
18.13.2
Non-Page mode
The data is multiplexed with the lower address byte and Address Strobe (ALE/AS, PD0) is
active in every bus cycle.
The PSD supports both modes. In Page mode, the PSD bus timing is identical to Non-Page
mode, except the address hold time and setup time with respect to Address Strobe
(ALE/AS, PD0) is not required. The PSD access time is measured from address (A7-A0)
valid to data invalid.
Table 40.
80C251 configurations
Configuratio
n
80C251 READ/WRITE
pins
Connecting to PSD pins
Page mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page mode, 80C31
compatible A7-A0 multiplex
with D7-D0
2
WR
PSEN only
CNTL0
CNTL1
Non-Page mode
A7-A0 multiplex with D7-D0
3
WR
PSEN only
CNTL0
CNTL1
Page mode
A15-A8 multiplex with D7-
D0
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page mode
A15-A8 multiplex with D7-
D0
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