參數(shù)資料
型號: PSD4256G6V-10UIT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 110/127頁
文件大?。?/td> 1091K
代理商: PSD4256G6V-10UIT
PSD4256G6V
I/O ports
19.6
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to Port A, B, C, D or F, and are routed as inputs to the PLDs. The address input can be
latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is
included in the DPLD equations for the primary Flash memory, secondary Flash memory or
SRAM is considered to be an address input.
19.7
Data Port mode
Ports F and G can be used as a data bus port for a MCU with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the MCU. The general I/O
functions are disabled in Ports F and G if the ports are configured as a Data Port. Data Port
mode is automatically configured in PSDsoft when a non-multiplexed bus MCU is selected.
19.8
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all
of Port F serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting bit 7 of the VM register to a 1. Figure 32 shows how Port A acts as a bi-
directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be specified in PSDsoft. The buffer is tri-stated when PSEL0 or
PSEL1 is not active.
Table 43.
I/O port latched address output assignments(1)
MCU
Port E
(PE3-PE0)
Port E
(PE7-PE4)
Port F
(PF3-PF0)
Port F
(PF7-PF4)
Port G
(PG3-PG0)
Port G
(PG7-PG4)
80C51XA
N/A(1)
Address
a7-a4
N/A
Address
a7-a4
Address
a11-a8
Address
a15-a12
80C251
N/A
Address
a11-a8
Address
a15-a12
All Other
MCUs with Multiplexed Bus
Address
a3-a0
Address
a7-a4
Address
a3-a0
Address
a7-a4
Address
a11-a8
(a3-a0 for 8-
bit MCU)
Address
a15-a12
(a7-a4 for 8-
bit MCU)
1.
N/A = Not Applicable.
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