參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 121/127頁
文件大?。?/td> 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
Power management
20.1
Automatic power-down (APD) Unit and Power-down mode
The APD Unit, shown in Figure 36, puts the PSD into Power-down mode by monitoring the
activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes High, and the PSD enters Power-down mode, as discussed next.
20.2
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the PSD is in Power-down mode:
●
If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal
operation. The PSD also returns to normal operation if either PSD Chip Select Input
(CSI, PD2) is Low or the Reset (RESET) input is High.
●
The MCU address/data bus is blocked from all memory and PLDs.
●
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the Power Management mode registers (PMMR). The
blocked signals include MCU control signals and the common CLKIN (PD1). Note that
blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit.
●
All PSD memories enter Standby mode and are drawing standby current. However, the
PLDs and I/O ports blocks do not go into Standby mode because you do not want to
have to wait for the logic and I/O to “wake-up” before their outputs can change. See
Table 50 for Power-down mode effects on PSD ports.
●
Typical Standby current is or the order of A. This standby current value assumes that
there are no transitions on any PLD input.
Table 50.
Effect of Power-down mode on ports
Port function
Pin level
MCU I/O
No change
PLD Out
No change
Address Out
Undefined
Data Port
Tri-state
Peripheral I/O
Tri-state
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