參數(shù)資料
型號(hào)： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 111/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
I/O ports
PSD4256G6V
Figure 32.
Peripheral I/O mode
19.9
JTAG in-system programming (ISP)
Port E is JTAG compliant, and can be used for in-system programming (ISP). You can
multiplex JTAG operations with other functions on Port E because in-system programming
(ISP) is not performed during normal system operation. For more information on the JTAG
19.10
MCU RESET mode
Ports F and G can be configured to operate in MCU RESET mode. This mode is available
when PSD is configured for the Motorola 16-bit 683xx and HC16 family and is active only
during reset.
At the rising edge of the RESET input, the MCU reads the logic level on the data bus (D15-
D0) pins. The MCU then configures some of its I/O pin functions according to the logic level
input on the data bus lines. Two dedicated buffers are usually enabled during RESET to
drive the data bus lines to the desired logic level.
The PSD can replace the two buffers by configuring Ports F and G to operate in MCU
RESET mode. In this mode, the PSD will drive the pre-defined logic level or data pattern on
to the MCU data bus when RESET is active and there is no ongoing bus cycle. After RESET,
Ports F and G return to the normal Data Port mode.
The MCU RESET mode is enabled and configured in PSDsoft. The user defines the logic
level (data pattern) that will be drive out from Ports F and G during RESET.
19.11
Port Configuration registers (PCR)
Each port has a set of Port Configuration registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal READ/WRITE bus
cycles at the addresses given in Table 6. The addresses in Table 6 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, bit 0 in a register refers to bit 0 of its port. The three Port
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0 - PA7
D0-D7
DATA BUS
AI02886
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