參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 48/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
Register bit definition
5
Register bit definition
All the registers of the PSD are included here for reference. Detailed descriptions of these
registers can be found in the following sections.
Table 7.
Data-In registers - Ports A, B, C, D, E, F, and G(1)
1.
Bit definitions (read-only registers): READ port pin status when port is in MCU I/O input mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Table 8.
Data-Out registers - Ports A, B, C, D, E, F, and G(1)
1.
Bit definitions: Latched data for output to port pin when pin is configured in MCU I/O output mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Table 9.
Direction registers - Ports A, B, C, D, E, F, and G(1)
1.
Bit definitions:
Portpin <i> 0 = Port pin <i> is configured in Input mode (default).
Portpin <i> 1 = Port pin <i> is configured in Output mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Table 10.
Control registers - Ports E, F, and G(1)
1.
Bit definitions:
Portpin <i> 0 = Port pin <i> is configured in MCU I/O mode (default).
Portpin <i> 1 = Port pin <i> is configured in Latched Address Out mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Table 11.
Drive registers - Ports A, B, D, E, and G(1)
1.
Bit definitions:
Portpin <i> 0 = Port pin <i> is configured for CMOS Output driver (default).
Portpin <i> 1 = Port pin <i> is configured for Open Drain output driver.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Table 12.
Enable-Out registers - Ports A, B, C, and F(1)
1.
Bit definitions (read-only registers):
Portpin <i> 0 = Port pin <i> is in tri-state driver (default).
Portpin <i> 1 = Port pin <i> is enabled.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Table 13.
Input Macrocells - Ports A, B, and C(1)
1.
Bit definitions (read-only registers):
READ input macrocell (IMC7-IMC0) status on Ports A, B, and C.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
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