參數(shù)資料
型號(hào)： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 50/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
Register bit definition
Table 21.
JTAG Enable register(1)
1.
Bit definitions:
JTAGEnable 1 = JTAG port is enabled.
JTAGEnable 0 = JTAG port is disabled.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
JTAGEnab
le
Table 22.
Page register(1)
1.
Bit definitions: configure Page input to PLD. Default is PGR7-PGR0 = '0.'
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGR 7
PGR 6
PGR 5
PGR 4
PGR 3
PGR 2
PGR 1
PGR 0
Table 23.
PMMR0 register(1)
1.
The bits of this register are cleared to zero following power-up. Subsequent Reset (RESET) pulses do not
clear the registers.
Bit definitions:
APD Enable
0 = Automatic power-down (APD) is disabled.
1 = Automatic power-down (APD) is enabled.
PLD Turbo
0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK
0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is
off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK
0 = CLKIN to the PLD macrocell is connected.
1 = CLKIN to the PLD macrocell is disconnected, saving power.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
PLD
MCells
CLK
PLD
Array CLK
PLD
Turbo
not used
(set to 0)
APD
Enable
not used
(set to 0)
Table 24.
PMMR2 register(1)
1.
For Bit 4, Bit 3, and Bit 2: see Table 34 and Table 35 for the signals that are blocked on pins CNTL0-
CNTL2.
Bit Definitions:
PLD Array Addr
0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
Note: In X A mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4.
PLD Array CNTL2
0 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1
0 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0
0 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE
0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH
0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
PLD
Array WRH
PLD
Array ALE
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to 0)
PLD
Array Addr
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