參數(shù)資料
型號： PSD4256G6V-10UIT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 46/127頁
文件大小： 1091K
代理商： PSD4256G6V-10UIT
PSD4256G6V
PSD register description and address offsets
4
PSD register description and address offsets
Table 6: Register address offset shows the offset addresses to the PSD registers relative to
the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by
the user to the internal PSD registers. Table 6 provides brief descriptions of the registers in
CSIOP space. The following sections give a more detailed description.
Table 6.
Register address offset
Register name
Port
A
Port
B
Port
C
Port
D
Port
E
Port
F
Port
G
Other(1)
Description
Data In
00
01
10
11
30
40
41
Reads port pin as input, MCU I/O input
mode
Control
32
42
43
Selects mode between MCU I/O or Address
Out
Data Out
04
05
14
15
34
44
45
Stores data for output to port pins, MCU I/O
output mode
Direction
06
07
16
17
36
46
47
Configures port pin as input or output
Drive Select
08
09
19
38
49
Configures port pins as either CMOS or
Open Drain
Input Macrocell
0A
0B
1A
Reads input macrocells
Enable Out
0C
0D
1C
4C
Reads the status of the output enable to the
I/O port driver
Output
Macrocells A
20
READ – reads output of macrocell A
WRITE – loads macrocell Flip-flops
Output
Macrocells B
21
READ – reads output of macrocell B
WRITE – loads macrocell Flip-flops
Mask
Macrocell A
22
Blocks writing to the output macrocells A
Mask
Macrocell B
23
Blocks writing to the output macrocells B
Flash Memory
Protection 1
C0
Read-only – Primary Flash Sector
Protection
Flash Memory
Protection 2
C1
Read-only – Primary Flash Sector
Protection
Flash Boot
Protection
C2
Read-only – PSD Security and secondary
Flash memory Sector Protection
JTAG Enable
C7
Enables JTAG port
PMMR0
B0
Power Management register 0
PMMR2
B4
Power Management register 2
Page
E0
Page register
VM
E2
Places PSD memory areas in Program
and/or data space on an individual basis.
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