參數(shù)資料
型號(hào): PSD4256G6V-10UIT
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁(yè)數(shù): 112/127頁(yè)
文件大小: 1091K
代理商: PSD4256G6V-10UIT
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PSD4256G6V
I/O ports
Configuration registers (PCR), shown in Table 44, are used for setting the port
configurations. The default Power-up state for each register in Table 44 is 00h.
19.12
Control register
Any bit reset to '0' in the Control register sets the corresponding port pin to MCU I/O mode,
and a 1 sets it to Address Out mode. The default mode is MCU I/O. Only Ports E, F and G
have an associated control register.
19.13
Direction register
The Direction register controls the direction of data flow in the I/O ports. Any bit set to 1 in
the Direction register causes the corresponding pin to be an output, and any bit set to 0
causes it to be an input. The default mode for all port pins is input.
Figure 33, Figure 34 and Figure 35 show the port Architecture diagrams for Ports A/B/C, D,
and E/F/G, respectively. The direction of data flow for Ports A, B, C and F are controlled not
only by the direction register, but also by the output enable product term from the PLD AND
Array. If the output enable product term is not active, the Direction register has sole control
of a given pin’s direction.
An example of a configuration for a port with the three least significant bits set to output and
the remainder set to input is shown in Table 47. Since Port D only contains four pins, the
Direction register for Port D has only the four least significant bits active.
19.14
Drive Select register
The Drive Select register configures the pin driver as Open Drain or CMOS. An external
pull-up resistor should be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is
set to a 1. The default pin drive is CMOS.
Table 48 shows the Drive register for Ports A, B, D, E and G. It summarizes which pins can
be configured as Open Drain outputs.
Table 44.
Port configuration registers (PCR)
Register name
Port
MCU access
Control
E, F, G
WRITE/READ
Direction
A, B, C, D, E, F, G
WRITE/READ
Drive Select(1)
1.
See Table 48 for Drive register bit definition.
A, B, D, E, G
WRITE/READ
Table 45.
Port pin Direction Control, Output Enable P.T. not defined
Direction register bit
Port pin mode
0
Input
1
Output
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