參數(shù)資料
型號: PSD4256G6V-10UIT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 8 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 122/127頁
文件大小: 1091K
代理商: PSD4256G6V-10UIT
Power management
PSD4256G6V
Figure 36.
APD unit
20.3
Other power saving options
The PSD offers other reduced power saving options that are independent of the Power-
down mode. Except for PSD Chip Select Input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2 (as summarized in Table 23 and Table 24).
20.4
PLD power management
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in PMMR0. By
setting the bit to 1, the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70ns. The propagation
delay time is increased after the Turbo bit is set to 1 (turned off) when the inputs change at a
composite frequency of less than 15MHz. When the Turbo bit is reset to '0' (turned on), the
PLDs run at full power and speed. The Turbo bit affects the PLD’s DC power, AC power, and
propagation delay. See the AC and DC characteristics tables in Section 25: DC and AC
parameters for PLD timing values.
Blocking MCU control signals with the PMMR2 bits can further reduce PLD AC power
consumption.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN) Select
DISABLE BUS
INTERFACE
Secondary Flash
Memory Select
Primary Flash
Memory Select
SRAM Select
PD
CLR
PD
DISABLE Primary and Secondary
FLASH Memory and SRAM
PLD
AI04939
Table 51.
PSD timing and standby current during Power-down mode
Mode
PLD propagation
delay
Memory
access time
Access recovery time to
normal access
Typical standby
current
Power-
down
Normal tPD
(1)
1.
Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the
Turbo bit.
No Access
tLVDV
50 A(2)
2.
Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
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