參數(shù)資料
型號(hào)： MC92604ZT
廠商： Freescale Semiconductor
文件頁數(shù)： 94/122頁
文件大?。?/td> 0K
描述： IC TXRX ETH DUAL GIG 196-MAPBGA
標(biāo)準(zhǔn)包裝： 630
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
System Design Considerations
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
5-5
5.6
Configuration and Control Signals
The MC92604 has many configuration and control signals that are asynchronous to all input clocks. Most
of the signals affect the internal configuration state and must be set at power up. If the signal’s state is
changed after power up, some signals require that the device be reset by asserting RESET low and then
releasing high. Other configuration signals are meant to be changed during normal operation and do not
require a device reset. However, these signals may still affect device operation. Table 5-3 lists all of the
MC92604 asynchronous configuration and control signals and describes the effect of changing their state
after power up.
If MDIO is enabled, then the states may be modified via the MDIO interface. When MDIO_EN is asserted,
the configuration states are loaded on reset as before, and may then be modified through the interface. The
configuration states are read via registers 1, 16, and 17. If any of the hardwired configurations change
when MDIO_EN is asserted, the device must be reset for the action to be initiated. For example, if
MDIO_EN is high, changing the configuration input, XCVR_x_LBE, will be ignored until reset is
asserted.
Table 5-3. Asynchronous Configuration and Control Signals
Signal Name
Description
Effect of Changed State
XCVR_x_DISABLE
Transceiver disable
Receiver must acquire new bit phase alignment;
byte and word synchronization must be
re-established.
XCVR_x_LBE
Transceiver loopback enable
Receiver must acquire new bit phase alignment;
byte and word synchronization must be
re-established.
DROP_SYNC
Drop synchronization
Receiver must re-establish byte and word
synchronization.
XMIT_REF_A
Transmitter reference clock A select
Device must be reset
RECV_REF_A
Receiver reference clock A select
Device must be reset
TBIE
Ten-bit interface enable
Device must be reset
HSE
Half-speed enable
Device must be reset
BSYNC
Byte synchronization mode
Device must be reset
ADIE
Add/drop idle enable
Device must be reset
JPAK
Expand receiver FIFO to tolerate Jumbo
packets
Device must be reset
COMPAT
Ethernet compatibility mode
Device must be reset
ENABLE_AN
Enable auto-negotiate
Device must be reset
RCCE
Recovered clock enable
Device must be reset
REPE
Repeater mode enable
Must be low and remain low during normal
operation. Device must be reset if changed.
WSYNC1
Word synchronization enable
Device must be reset
WSYNC0
Word synchronization enable
Device must be reset
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