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| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 63/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Receiver
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
3-11
When word synchronization is lost it must be re-established before data flow through the receiver resumes.
The receiver interface is disabled during initial word alignment. No data is produced at its outputs until
word alignment is achieved and a word synchronization event has been detected. When establishing word
synchronization, or when word synchronization is lost, ‘not word sync’ error is reported as described in
Word synchronization is possible in byte interface mode and TBI mode. However, word synchronization
may be dependent on the detection of simultaneously transmitted word synchronization events that contain
Idle characters. Therefore, if operating in TBI mode, either the Idle character must be a supported member
of the code set or the ‘A’ character alignment must be used.
3.6
Receiver Interface Timing Modes
The receiver interface is timed to the recovered clock (link partner’s clock) or to the reference clock (local
clock), depending on the state of the recovered clock enable, RCCE, signal. RCCE enables timing relative
to the recovered clock when asserted and enables timing relative to the reference clock when negated.
The receiver interface clock signals, RECV_x_RCLK, will always be present when the PLL is in lock. This
is true even if there is no signal present on the serial inputs or if the receiver has not achieved alignment
or byte sync. The frequency of the receiver clock will be the local reference clock until synchronization is
achieved. The RECV_x_RCLK clock signals, however, are not present during power up or when the
MC92604 is in reset mode and the PLL is not locked.
All receiver channels data outputs are source synchronous with their respective RECV_x_RCLK outputs.
They may be configured to be source aligned or source centered with their respective RECV_x_RCLK
outputs. The configuration signal, RECV_CLK_CENT, when asserted high, will center the receiver clocks
relative to the data and status outputs.
NOTE
The receiver clock complement, RECV_x_RCLK_B, is only provided in
the TBIE/RTBI Ethernet compliant application modes (TBIE and
COMPAT = high). If either TBIE or COMPAT is low, then
RECV_x_RCLK_B is always low.
3.6.1
Recovered Clock Timing Mode (RCCE = High)
With RCCE asserted, the receiver clock signal, RECV_x_RCLK, is generated by the receiver and, on
average, runs at the reference clock frequency of the transmitter (link partner’s clock) at the other end of
the link. The recovered clock is not generated by a clock recovery PLL but by monitoring the receive
FIFO.
When RCCE is high, the configuration signal, RECV_REF_A, is used to select the clock to be used. If
RECV_REF_A is high, channel A’s recovered clock is used for both channels. If it is low, then each
channel uses its own recovered clock. If RECV_REF_A is high, it is assumed that both channels are
operating at an identical frequency.
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