參數(shù)資料
型號： MC92604ZT
廠商： Freescale Semiconductor
文件頁數(shù)： 107/122頁
文件大?。?/td> 0K
描述： IC TXRX ETH DUAL GIG 196-MAPBGA
標(biāo)準(zhǔn)包裝： 630
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 2/2
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
Electrical Specifications and Characteristics
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
7-3
7.2
DC Electrical Specifications
This section describes the MC92604 DC electrical characteristics as provided in Table 7-3.
Table 7-3. DC Electrical Specifications
Characteristic1
1 Unless otherwise noted: V
DD = AVDD = VDD = 1.8 + 0.15 V DC, VDDQ = 3.3 + 0.3 V DC, GND = 0 V DC, –40° < Tj < 105° C.
Symbol
Min
Typ
Max
Unit
Core supply current 2
2 Maximum currents at V
DD = AVDD = XVDD = 1.95 V DC, VDDQ = 3.6 V DC, all links operating at full-speed. Typicals are with
nominal supply voltages.
IDD
—
200
225
mA
PLL supply current 2
AIDD
—
8
10
mA
LVCMOS/TTL I/O supply current 2
IDDQ
—
35
45
mA
Link I/O supply current 2
XIDD
—
70
90
mA
Total power dissipation 3
3 Typical P
D (mWatts) = A + Bn + Cnf + Df; where n = number of active channels and f = reference frequency in MHz. Note: A,
B, C, and D are to be determined (TBD).
PD
—
550
720
mW
LVCMOS/TTL input high voltage
VIH
1.7
—
VDDQ + 0.3
V
LVCMOS/TTL input low voltage
VIL
–0.3
—
0.7
V
LVCMOS/TTL input leakage current, Vin = VDDQ
IIH
—
+10
A
LVCMOS/TTL input leakage current, Vin = GND
IIL
—
+10
A
LVCMOS/TTL output high voltage, IOH = –7.6 mA
VOH
1.76
—
V
LVCMOS/TTL output low voltage, IOL = 7.6 mA
VOL
—
0.54
V
LVCMOS/TTL output high voltage, IOH = –2 mA
VOH
2.0
—
V
LVCMOS/TTL output low voltage, IOL = 2mA
VOL
—
0.4
V
LVCMOS/TTL input capacitance
Cin
—
10
pF
LVCMOS/TTL output impedance, Vout = VDDQ/2
Rout
—
50
—
W
LVPECL AC differential input voltage
VPKPK
0.4
—
1.3
V
LVPECL differential cross point voltage
VCMR
1.25
—
VDDQ – 0.3
V
LVPECL input current
IIN
—
+100
A
Link common mode input impedance
Rcm
2
—
4
K
Link differential input impedance (MEDIA = low/high)
Rdiff
85/127.5
—
130/195
W
Link common mode input level4
4 Subject to absolute voltage on link input pin remaining in recommended range per Table 7-2.
Vcm
0.725
—
1.225
V
Link differential input amplitude
V
in
0.4
—
3.2
Vp-p
Link input capacitance
Cin
—
3
pF
Link common mode output level
Vcm
0.725
0.9
1.075
V
Link differential output amplitude,
(100/150
diff load, MEDIA = low/high)
V
out
1.3
—
2.2
Vp-p
Link differential output impedance (MEDIA = low/high)
Rout
—
100/150
—
W
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