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| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 43/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Transmitter
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
2-5
disparity is maintained, and the appropriate transmission characters are produced, maintaining DC balance
and sufficient transition density to allow reliable data recovery at the receiver. The 8B/10B encoder is
bypassed if TBIE is asserted high.
The transmitter data interface operates at high frequency (nominally 125 MHz). In order to ease
development of devices that interface with the Gigabit Ethernet transceiver, all transmitter data input
interfaces are source-synchronous. The data for each channel has its own dedicated clock input. This
allows the clock at the source of the data to be routed with the data ensuring matched delay and timing.
However, if per-channel clock sources are not available or deemed unnecessary, all channels may be
clocked by a common clock source. This is enabled by asserting XMIT_REF_A high. When
XMIT_REF_A is high, the XMIT_A_CLK becomes the interface clock for all active channels.
The configuration settings of the MC92604 affect the legal range of clock frequencies at which it may be
operated. Table 5-1 shows legal transmit interface clock frequencies for all modes of operation. All
transmit interface clock inputs, XMIT_x_CLK, and the PLL reference clock inputs, REF_CLK, must have
identical frequencies. The transmit data interface tolerates
±180° of transmit interface clock phase drift
relative to the PLL reference clock input.
2.3.1
Transmit Driver Operation
The transmit driver outputs the transmission characters serially across the link. Two bits per internal
transceiver clock, rx_clock, one each on the rising and falling clock edges, are transmitted differentially
from the XLINK_x_P/XLINK_x_N outputs. The internal rx_clock runs at 625 MHz for 1-Gbps
(1.25-Gbaud) operation and 312.5 MHz for 500-Mbps (625-Mbaud) operation.
The transmitter driver (high-speed serial link outputs) is a controlled impedance driver. The impedance of
the driver is programmable to 50 or 75
through the MEDIA configuration signal. The drive impedance
is 50
when MEDIA is low and 75 when high.
2.3.2
Repeater Mode Operation
Although repeater mode is primarily used for factory engineering, it may be used by the application as
described in Section 5.5, “Repeater Mode.” The repeater enable signal, REPE, should be configured low
during a normal transceiver operation.
2.4
Backplane Application Modes (COMPAT = Low)
When the configuration control signal, COMPAT, is low, the MC92604 is in the ‘backplane application
mode.’ In this application mode, the MC92604 transmitters accept either uncoded data, where the input
data is encoded internally by an 8B/10B encoder, or coded data, where the input data is pre-encoded and
the internal encoder is bypassed.
The interface for the backplane application mode is either 8 or 10 bits wide, or optionally 4 or 5 bits, as
shown in Table 2-2.
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