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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 102/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤(pán) |
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Test Features
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
6-4
Freescale Semiconductor
6.2.1
Loopback System Test
Each channel of MC92604 may be individually configured for digital loopback, where the transmitted data
is looped back to its receiver independent of the receiver’s link inputs. This is enabled by asserting
XCVR_x_LBE (where ‘x’ is channel A or B) high. The code groups transmitted are controlled by the
normal transmitter controls. If the transceiver is working properly, the data/control code groups
transmitted are received internally by the receiver. This allows system logic to use various data sequences
to test the operation of the transceiver.
The loopback signals are electrically isolated from the XLINK_x_P and XLINK_x_N output signals.
Therefore, if the outputs are externally shorted, or otherwise restricted, the loopback signals still function
normally. When in loopback mode, the XLINK_x_P and XLINK_x_N output signals will continue to
operate normally.
The receiver’s link input signals, RLINK_x_P and RLINK_x_N, are electrically isolated during loopback
mode, such that their state does not affect the loopback path.
LBOE controls the state of the XLINK_x_P/XLINK_x_N output signals during loopback testing. If LBOE
is low, XLINK_x_P/XLINK_x_N are held to low and high, respectively. If LBOE is high, data is present
on XLINK_x_P/XLINK_x_N.
6.2.2
BIST Sequence System Test with External Loopback Modes
The MC92604’s transmitter has an integrated, 23rd order, pseudo-noise (PN) pattern generator. Stimulus
from this generator may be used for system testing. The receiver, has a 23rd order signature analyzer that
is synchronized to the incoming PN stream and may be used to count code group mismatch errors relative
to the internal PN reference pattern.
This implementation of the 23-bit PN generator and analyzer uses the following polynomial:
f = 1 + x5 + x23
The total mismatch error count is reset to zero on entering BIST mode. The count is updated continuously
while in BIST mode. The value of the count is presented on the receiver interface signals,
RECV_x_7–RECV_x_0, which make up the 8-bit error count. The value of the count is sticky in that the
count will not wrap to zero on overflow, but rather, stays at the maximum count value (11111111).
NOTE
An error counter is maintained in MDIO RA 18 for each specific channel in
details.
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