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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 62/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Receiver
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
3-10
Freescale Semiconductor
3.5.3
Word Synchronization
When the MC92604 is configured in either of the ‘a(chǎn)ligned backplane’ modes (BSYNC high and COMPAT
low), the two receivers can be used cooperatively to receive 16-bit (20-bit if TBIE is high) aligned word
transfers. Word alignment is enabled by asserting the word synchronization enable inputs, WSYNC1 or
WSYNC0, high.
3.5.3.1
Word Synchronization Method
The word synchronization aligns code groups in the receiver’s alignment FIFO. Synchronization is
accomplished by lining up word synchronization events detected by each of the receivers, such that all are
coincident at the same output stage of their FIFO.
There are three word synchronization events as defined in Table 3-5.
The 4/1 IDLE sequence is defined as four consecutive IDLE code groups followed by a non-IDLE code
group. The disparity-based IDLE sequence is 16 consecutive IDLE code groups with improper disparity
on the second and third IDLE code group in the sequence. The disparity-based IDLE sequence is described
further in Section 2.4.1, “Transmitting Uncoded Data—8-/4-Bit Modes.” Optionally the special control
character K28.3 (/A/) may be used as a word synchronization event.
Word synchronization events must be generated at all concerned transmitters simultaneously in order for
synchronization to be achieved. Word synchronization events must be received at all concerned receivers
within 40 bit-times of each other.
Word synchronization events are used to establish a relationship between the received bytes in each of the
receivers. The bytes of a word are matched and presented simultaneously at the receiver interface. Once
synchronization is achieved the receiver tolerates +6 bit-times of drift between receivers. If drift exceeds
+6 bit-times the receiver will continue to operate. However, the received bytes will no longer be
synchronized properly because the receiver remains locked on the initially established synchronization.
Word synchronization remains locked until one of three events occur that indicate loss of synchronization.
Word synchronization lock is lost when one or more of the receivers lose or change byte alignment.
Byte alignment loss is described in Section 3.5.2, “Byte-Aligned Mode (BSYNC = High).”
Lock is also lost when overrun/underrun is detected on one or more of the receivers, see Section
Finally, both byte and word synchronization are lost when explicitly invalidated by asserting
XCVR_x_DISABLE high. Word synchronization lock is lost when explicitly invalidated by
asserting DROP_SYNC and XCVR_x_DISABLE high for at least two clocks (see Section 3.5.2,
Table 3-5. Word Synchronization Events
Word Synchronization Event
WSYNC1
WSYNC0
No word synchronization required
Low
4 IDLE/1 non-IDLE
Low
High
Disparity-based IDLE sequence
High
Low
Align to special control character K28.3 (/A/)
High
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