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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 108/122頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤(pán) |
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Electrical Specifications and Characteristics
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
7-4
Freescale Semiconductor
7.3
AC Electrical Characteristics
The figures and tables in the following sections describe the AC electrical characteristics of MC92604. All
specifications stated are for Tj = –40° to 105°C, VDD = AVDD = XVDD = 1.65 to 1.95 V, VDDQ = 3.0 to 3.6 V
7.3.1
Transmitter Interface Timing
The transmitter data interface may be configured in any of eight different application modes as described
in Section 2.2, “Transmitter Interface Signals,” and Table 2-2. The 8- and 10-bit interface mode timing is
non-double data rate (non-DDR); the input data is sampled and stored on the rising edge of the transmit
interface clock XMIT_x_CLK.
When operating in the reduced 4- or 5-bit backplane, or RGMII/RTBI Ethernet modes, the interface is
double data rate (DDR) and the data is sampled and stored on both the rising and falling edges of the
transmit interface clock XMIT_x_CLK.
The following two sections show the timing diagrams and specifications for the transmitter in the
non-DDR and DDR configurations.
7.3.1.1
Transmitter Interface, Non-DDR Timing
Figure 7-1 provides the transmitter interface non-DDR interface timing diagram.
Figure 7-1. Transmitter Interface, Non-DDR Timing Diagram
Table 7-4 provides the transmitter non-DDR timing specifications for the MC92604 as defined in
Table 7-4. Transmitter Non-DDR Timing Specification
Symbol
Characteristic
Min
Max
Unit
Application Mode
T1
Setup time prior to rising edge of XMIT_x_CLK
1.000
—
ns
All modes
T2
Hold time after rising edge of XMIT_x_CLK
0.01
1 Synchronous to channel’s transmit interface clock; XMIT_REF_A = low.
—
ns
GMII or TBI
0.200 1
—
ns
Backplane modes
0.6002
2 Synchronous to XMIT_A_CLK; XMIT_REF_A = high.
—
ns
All modes
Φ
drift
Phase drift between XMIT_x_CLK and REF_CLK
–180
180
degrees
All modes
T2
XMIT_x_CLK
XMIT_x_7–0
XMIT_x_K
XMIT_x_ERR
XMIT_x_ENABLE
T1
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