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| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 85/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Management Interface (MDIO)
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
4-9
4.2.9
MDIO RA 16 (Vendor Specific)—Permanent Configuration Control
Register
MDIO RA 16 is vendor specific and contains the MC92604 permanent configuration control register.
These bits are initially loaded from the states of the corresponding configuration input pins. They may be
modified through the MDIO interface, but if they are written through this interface, the logic within the
MC92604 is reset, and normal operations will be interrupted until individual channels are resynchronized.
Figure 4-8 shows the content of register 16.
NOTE
Only one copy of this register exists within GEt. It may be accessed through
either channel, but if modified it affects operation of both channels.
Table 4-6 lists the corresponding field descriptions for the permanent configuration register.
15
14
13
12
11
10
9
8
R
xmit_ref_a
recv_ref_a
tbie
bsync
compat
rcce
repe
wsync1
W
Reset XMIT_REF_A
RECV_REF_A
TBIE
BSYNC
COMPAT
RCCE
REPE
WSYNC1
7
6
5
4
3
2
1
0
R
wsync0
jpack
adie
tst_1
tst_0
lboe
use_short_
an_timer
ddr
W
Reset
WSYNC0
JPACK
ADIE
TST_1
TST_0
LBOE
0
DDR
Figure 4-8. Permanent Configuration Control Register (MDIO RA 16)
Table 4-6. Permanent Configuration Control Register
Field Descriptions
Bits
Name
Description1
15
xmit_ref_a_reg
Initialized to the value on the XMIT_REF_A input. If set, indicates that all transmit data into the
transmitter is synchronous with channel A’s transmit clock (XMIT_A_CLK). (R/W)
14
recv_ref_a_reg
Initialized to the value on the RECV_REF_A input. If set, indicates that all receive data out of
the receiver is synchronous with channel A’s recovered clock (RECV_A_RCLK). (R/W)
13
tbie_reg
Initialized to the value on the TBIE input. If set, indicates that data into the transmitter and out
of the receiver is to be treated as ten-bit coded data. (R/W)
12
bsync_reg
Initialized to the value on the BSYNC input. If set, indicates that data out of the receiver is to be
byte aligned using COMMA code groups. (R/W)
11
compat_reg
Initialized to the value on the COMPAT input. If set, indicates that if context sensitive, data will
be dropped or repeated to prevent overrun/underrun. See Chapter 5, “System Design
” for an explanation. (R/W)
10
rcce_reg
Initialized to the value on the RCCE input. If set, indicates that the received data clock frequency
should be at the ‘recovered’ clock rate. If reset, then receive data frequency is derived from the
‘reference’ clock. See Section 3.6.1, “Recovered Clock Timing Mode (RCCE = High)” and
Section 3.6.2, “Reference Clock Timing Mode (RCCE = Low),” for an explanation. (R/W)
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