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| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 78/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤(pán) |
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Management Interface (MDIO)
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
4-3
4.2.1
MDIO RA 0—Control Register
Figure 4-1 shows the format for the control register, MDIO RA 0, in the MC92604.
Table 4-2 lists the corresponding field descriptions for the control register.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PHY
Reset
Loop-
back
Speed
Select
[0]
Auto-
Negotiation
Enable
Power
Down
Isolate
Restart
Auto-
Negotiation
Duplex
Mode
Collision
Test
Speed
Select
[1]
Reserved
W
Reset
1/0
XCVR_
x_LBE
0
ENABLE_AN
0
1
0
1
0 0 0 0 0 0
Figure 4-1. Control Register (MDIO RA 0)
Table 4-2. Control Register (MDIO RA 0) Field Descriptions
Bits
Name
Description1
1 R = read-only, R/W = read and write, and SC = self-clearing.
15
Reset
Bit 15 may be written through the MDIO interface. It is initialized to zero on power up or
a device reset. When set, it forces the other MDIO registers to be loaded with their
default value. This bit is automatically reset (self-clearing) one clock after it is set. (R/W,
SC)
14
Loopback
Initialized to the value on the XCVR_x_LBE input. When set, it forces a digital loopback
on the transceiver interface. When a channel is in loopback mode, data transmitted into
the transmit interface is looped back on the serial link input to the same channel’s
receiver. (R/W)
13
Speed select [0]
Bit 13 is forced to zero and may not be modified. MC92604 is always configured as a
1-gigabit device. (R)
12
Auto-negotiation enable
Bit 12 is initialized to the value on the ENABLE_AN input, but may be modified through
the MDIO interface. (R/W)
11
Power down
Bit 11 is forced to zero and may not be modified. MC92604 does not support power
down. (R)
10
Isolate
Bit 10 is forced to zero and may not be modified. MC92604 does not support isolation
of the GMII interface through the MDIO interface. Such isolation is available through the
JTAG controller. (R)
9
Restart auto-negotiation
Bit 12 is initialized to zero but may be modified. If set, the auto-negotiation sequence is
started (re-started). (R/W)
8
Duplex mode
Bit 8 is forced to one and may not be modified. MC92604 always runs in full-duplex
mode. (R)
7
Collision test
Bit 7 is forced to zero and may not be modified. MC92604 does not run in half-duplex
mode and, therefore, does not detect collisions. (R)
6
Speed select [1]
Bit 6 is forced to one and may not be modified. MC92604 is always configured as a
1-gigabit device. (R)
5–0
Reserved
Bits 5–0 are unused in the MC92604 application. They may not be modified. (R)
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