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| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 82/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標準包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Management Interface (MDIO)
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
4-6
Freescale Semiconductor
4.2.4
MDIO RA 4—Auto-Negotiation Advertisement Register
Figure 4-4 shows the format for the auto-negotiation (AN) advertisement register, MDIO RA 4, in the
MC92604.
NOTE
The ‘Ack’ bit is set when three consecutive matching configuration registers
are received. The auto-negotiation state is complete when three consecutive
matching configuration registers are received with the ‘Ack’ bit set. The
transmitter will continue sending auto-negotiation sequences once the
auto-negotiation sequence is complete for at least 10 ms.
Table 4-4 lists the corresponding field descriptions for the AN advertisement register.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Next
Page
Acknowledge
Remote
Fault 2
Remote
Fault 1
Reserved
Pause 2
Pause 1
Half-
Duplex
Full-
Duplex
Reserved
W
Reset
0
1/0
0
0/1
0
1
0 0 0 0 0
Figure 4-4. Auto-Negotiation (AN) Advertisement Register (MDIO RA 4)
Table 4-4. AN Advertisement Register (MDIO RA 4) Field Descriptions
Bits
Name
Description1
1 R = read-only, R/W = read and write.
15
Next page
Forced to zero. The MC92604 does not support multiple pages of configuration registers.
(R)
14
Acknowledge
Ack—is set when the receiver detects a valid configuration from the link partner’s
transmitter. (R)
13
Remote fault 2
Bits 13 and 12 are remote faults as detected by the receiver. (R)
RF1
RF2
Interpretation
0
Link is okay
12
Remote fault 1
0
1
Offline (XCVR_x_DISABLE is high)
1
0
Link failure (receiver is not byte-synced)
1
Link failure during auto-negotiation (receiver is not
byte-synced during the auto-negotiation sequence)
11–9
Reserved
Forced to zero and may not be modified. (R)
8
Pause 1
PS1 and PS2—Pause control bits that are modified through the MDIO interface by MAC.
(R/W)
7
Pause 0
6
Half-duplex
Forced to zero. The MC92604 does not support half-duplex mode. (R)
5
Full-duplex
Forced to one. The MC92604 always runs in full-duplex mode. (R)
4–0
Reserved
Forced to zero
and may not be modified. (R)
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