參數資料
型號: MC92604ZT
廠商: Freescale Semiconductor
文件頁數: 32/122頁
文件大小: 0K
描述: IC TXRX ETH DUAL GIG 196-MAPBGA
標準包裝: 630
類型: 收發(fā)器
驅動器/接收器數: 2/2
規(guī)程: 千兆位以太網
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 196-LBGA
供應商設備封裝: 196-MAPBGA(15x15)
包裝: 托盤
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
1-1
Chapter 1
Introduction
This chapter consists of the following sections:
This reference manual explains the functionality of the MC92604 Dual transceivers (GEt) and enables its
use by software and hardware developers. The audience for this publication, therefore, consists of
hardware designers and application programmers who are building data path switches and high-speed
backplane intercommunication applications.
1.1
Overview
The Gigabit Ethernet transceiver was designed with the intent to meet the requirements of IEEE Std.
802.3—2002. It was designed to fully support full-duplex GMII or TBI PHY applications including the
reduced RGMII or RTBI defacto interfaces. Each channel also has its own independent MDIO register set
as specified in the above standard.
The MC92604 GEt is designed as four parts in one. It may be configured as either a 1 Gigabit backplane
serializer/deserializer (SerDes) with functionally similar to the 1.25 Gbaud Quad SerDes (MC92600), or
as a Dual 1 Gigabit Ethernet PHY and the reduced interface versions of these two.
The GEt is a high-speed, full-duplex, serial data interface device that can be used to transmit data between
chips across a board, through a backplane, or through cabling, as well as to interface to GBIC/SFP
modules. The multi-channel device has transceivers that transmit and receive coded data at a rate of
1.0 Gbps through each 1.25 gigabaud link.
The MC92604 is built on the proven transceiver technology of the MC92600 and MC92602 devices.
Carefully designed for low-power consumption, its CMOS implementation nominally consumes less than
1 W with all links operating at full speed when in the backplane interface mode.
The MC92604 features transmit FIFOs and source synchronous transmit clocks per channel to further
simplify interfacing. Additionally, IEEE Std 1149.1—1990 JTAG boundary scan and built-in PRBS
generator/analyzers are provided for board test support.
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