參數(shù)資料
型號： MC92604ZT
廠商： Freescale Semiconductor
文件頁數(shù)： 58/122頁
文件大?。?/td> 0K
描述： IC TXRX ETH DUAL GIG 196-MAPBGA
標準包裝： 630
類型： 收發(fā)器
驅動器/接收器數(shù)： 2/2
規(guī)程： 千兆位以太網
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應商設備封裝： 196-MAPBGA（15x15）
包裝： 托盤
Receiver
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
3-6
Freescale Semiconductor
3.3.2
Transition Tracking Loop and Data Recovery
The received differential data from the input amplifier is sent to the transition tracking loop for data
recovery. The MC92604 uses an oversampled transition tracking loop method for data recovery.
The differentially received data is sampled and processed digitally to provide for low-bit error rate (better
than 10–12).
The transition tracking loop is tolerant of frequency offset between the transmitter and receiver. The
MC92604 reliably operates with +250 ppm of frequency offset. The transition tracking loop method is
different than the typical PLL clock recovery method. Its receiver compensates for overrun and underrun
due to frequency offset. The receiver does this by modulating the duty-cycle and period of the received
byte clock so that it matches the frequency of the received data (see Section 3.6.1, “Recovered Clock
Timing Mode (RCCE = High),” for more information).
Recovered data is accumulated into 10-bit characters. If a byte alignment mode is enabled by asserting
BSYNC high, the characters are aligned to their original 10-bit boundaries.
3.3.3
8B/10B Decoder
The 8B/10B decoder takes the 10-bit character from the transition tracking loop and decodes it according
to the 8B/10B coding standard [1,2]. The decoder does two types of error checking. First, it checks that all
characters are legal members of the 8B/10B coding space. The decoder also checks for running disparity
errors. A disparity error is generated if the running disparity exceeds the limits set in the 8B/10B coding
standard.
An illegal character or disparity error asserts the RECV_x_ERR signal high, coincident with the received
data for a 1-byte output period. The ‘code error’ or ‘disparity error’ is being reported as described in
Table 3-9 and Table 3-14. It is difficult to determine the exact byte that causes a disparity error, so the error
should not be associated with a particular received byte. Rather, it is a general indicator of the improper
operation of the link. Use of the disparity error is provided so the system can monitor link reliability.
The 8B/10B decoder is bypassed when operating in 10-bit interface mode (TBIE asserted high).
3.3.4
Half-Speed Mode
Half-speed mode, enabled when HSE is asserted high, operates the receiver in its lower speed range. In
half-speed mode, the link speed is 500 Mbps (625 Mbaud). The receiver interface operates at half-speed
as well, in pace with the received data.
3.3.5
Repeater Mode
Although repeater mode is primarily used for factory engineering, it may be used by the application, as
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