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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 91/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤(pán) |
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System Design Considerations
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
5-2
Freescale Semiconductor
The internal reference clock may be driven by either a 3.3-V (LVTTL) input (TTL_REF_CLK) or by a
pair of LVPECL differential inputs (REF_CLK_P and REF_CLK_N). If the USE_DIFF_CLOCK input is
high, the LVPECL differential inputs, REF_CLK_P and REF_CLK_N, are used as the clock source. If
USE_DIFF_CLOCK is low, the TTL_REF_CLK input is used as the clock source.
The differential reference clock inputs, REF_CLK_P/N, may also be driven by a single-ended source. The
REF_CLK_N input must be set at VREF = 1.25 V for a single-ended operation of REF_CLK_P and must
be connected to its own reference voltage circuit.
When using the differential LVPECL inputs, the unused input, TTL_REF_CLK, shall be terminated low.
When using the single-ended TTL input, the differential LVPECL reference clock inputs shall be
terminated low.
5.2
Startup
The MC92604 begins a startup sequence on application of the reference clock input to the device. This is
considered a cold startup. The cold startup sequence is as follows:
1. PLL startup
2. Receiver initialization and byte alignment
3. Word alignment (if enabled)
4. Run
The expected duration of each step in the startup sequence is shown in Table 5-2. A cold startup can be
initiated at any time by negating RESET low. It is recommended that RESET be low at initial startup, but,
it is not strictly required.
5.3
Standby Mode
Standby mode puts the MC92604 into a low power, inactive state. When STNDBY is asserted high, the
device will force all transmitter link outputs to their disabled state as defined in Section 2.3.1, “Transmit
Driver Operation,” and disables all internal clocking. An important feature of standby mode is that the
internal PLL is not disabled. It remains operating and locked to the reference clock. This greatly reduces
the time needed to recover from standby mode to run mode, as only the receiver initialization and word
alignment startup steps are required.
Table 5-2. Startup Sequence Step Duration
Startup Step
Typical Duration
(in Bit Times)
Notes
PLL startup
20480 + 25
s
Receiver initialization
300
WSYNC1 and WSYNC0 = low
Word alignment
160
WSYNC1 or WSYNC0 = high
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