MC68F375
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
4-15
4.3.6.1 Frequency control Bits (X,W,Y)
Bits [15:8] of the SYNCR control the multiplication or division factors of the synthe-
sizer. X bit [15] controls a one-bit divider which drives the system clock in all modes.
When X is set, the divider is bypassed; when clear, the system clock is divided by two.
The W bits and the Y bits have different field lengths and functions depending on the
clock mode. In slow reference mode, bit [14] is the single W bit, and bits [13:8] are the
six Y bits, and both fields are used to multiply the reference frequency. In fast refer-
ence mode, bits [14:12] are the three W bits, which are used to multiply the reference
frequency. Bits [10:8] are the three Y bits, which are used to divide the PLL output fre-
quency. In external clock mode, bits [14:11] are unused, and bits [10:8] are the three
Y bits which are used to divide the input clock frequency. Refer to Table 4-6 and Table 4-7 for system frequencies available in common configurations.
4.3.6.2 E Clock Divide Rate (EDIV)
The E clock that goes to the chip select section is driven from a divider circuit off of the
same clock source that drives the external clock. This allows turning off or leaving on
the E clock in LPSTOP mode using the STEXT bit. When EDIV=0, E is the system
clock divided by eight. When EDIV=1, E is the system clock divided by 16. EDIV is
cleared to zero by reset.
4.3.6.3 Loss of Clock Oscillator Disable (LOSCD)
An internal oscillator is used in the detection of loss of clock. This oscillator can be dis-
of this feature. When LOSCD = 1, the loss of clock oscillator is disabled. When LOSCD
= 0, the loss of clock oscillator is enabled. This bit is cleared to 0 on reset.
4.3.6.4 Limp Mode (SLIMP)
This read only status bit indicates whether the loss of crystal detect logic has detected
a loss of system clock. If a loss of clock is detected, the synthesizer will use an internal
RC oscillator to derive the system clock and enter limp mode, allowing the MCU to
continue to run even without an external clock.
SLIMP=0 indicates that the system clock is being provided normally, either by the PLL
or by an external clock from the EXTAL input. SLIMP=1 indicates that a loss of system
clock has been detected, and the system clock is being provided from the loss of crys-
clock is approximately 16 KHz.
SYNCR — Synthesizer Control Register, External Clock Mode
0xYF FA04
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
X
Reserved
Y
EDIV
Re-
served
LOSCD
SLIMP
SLOCK
RSTEN
STSCIM
STEXT
RESET:
1
0
1
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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