MC68F375
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
4-55
4.7.2 Reset Exception Processing
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the
exception vector table. The exception vector table consists of 256 four-byte vectors
and occupies 1024 bytes of address space. The CPU32 uses vector numbers to cal-
information.
Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset
occurs at the end of a bus cycle and not at an instruction boundary. Handling resets in
this way prevents write cycles in progress at the time the reset signal is asserted from
being corrupted. However, any processing in progress is aborted by the reset excep-
tion and cannot be restarted. Only essential reset tasks are performed during
exception processing. Other initialization tasks must be accomplished by the excep-
tion handler routine.
NOTE
External circuitry is required to disable external bus configuration
logic until DS and R/W are negated to ensure that bus cycles in
progress at the time RESET is asserted complete correctly.
4.7.3 Reset Source Summary
SCIM2E reset control logic determines the cause of a reset, synchronizes request sig-
nals to CLKOUT, and asserts reset control logic. All resets are gated by CLKOUT.
Asynchronous resets can occur on any clock edge and are assumed to be cata-
strophic. Synchronous resets are timed to occur at the end of bus cycles. When a
synchronous reset is detected, the SCIM2E bus monitor is automatically enabled. If
the bus cycle during which a synchronous reset is detected does not terminate nor-
mally, the bus monitor will terminate the cycle and allow the reset to proceed. Table 4-22 is a summary of reset sources.
Table 4-22 Reset Source Summary
Type
Source
Timing
External
Assertion of RESET pin
Synchronous
Power on
Rising voltage on VDD
Asynchronous
Software watchdog
Timeout of software watchdog
Asynchronous
Halt
Halt monitor (e.g. double bus fault)
Asynchronous
Loss of clock
Reference failure caught by loss of clock detector
Synchronous
Test
Test submodule
Synchronous
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